NVLink 6.0<\/td> 2026<\/td> Vera Rubin<\/td> up to 36<\/td> 3.6 TB\/s<\/td> Bidirectional SerDes<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\nThe signaling trend is easy to spot. Early NVLink generations used NRZ encoding and modest per-lane rates, then NVIDIA moved to PAM4 signaling at NVLink 4.0 and kept raising the rate per lane. NVLink 6 doubles the per-GPU link count to as many as 36 and moves to bidirectional SerDes, the same high-speed electrical signaling class now appearing across 1.6T Ethernet optics. That is why the physical layer of NVLink now overlaps directly with the optical transceiver industry.<\/p>\n\n\n\n
<\/span>Topology Evolution: How GPU Networks Grew<\/strong><\/strong><\/span><\/h2>\n\n\n\nThe most important change across generations is not raw speed; it is topology. Every generation changed how GPUs are wired together.<\/p>\n\n\n\n
<\/span>Direct GPU-to-GPU Mesh (No Switch)<\/strong><\/strong><\/span><\/h3>\n\n\n\nThe first NVLink products connected GPUs directly to their neighbors. The Tesla P100 and Volta V100 attached up to four and six links respectively to nearby GPUs, forming a small mesh. This worked for systems with a handful of GPUs but could not scale, because adding GPUs forces each one to carry more links. The DGX-1, which held eight V100 GPUs, used a hybrid cube-mesh arrangement that kept all eight GPUs connected without a switch.<\/p>\n\n\n\n
<\/span>The First NVSwitch Fabric (2018)<\/strong><\/strong><\/span><\/h3>\n\n\n\nNVIDIA reached the scaling limit of direct meshes with the DGX-2 in 2018, which packed 16 V100 GPUs. Instead of wiring every GPU to every other GPU, NVIDIA introduced NVSwitch. The DGX-2 carried six first-generation NVSwitch ASICs on each of its two baseboards, and each GPU talked to the switch fabric instead of to every peer. Every GPU pair could then communicate at full NVLink speed, and the system behaved as a single 16-GPU domain.<\/p>\n\n\n\n<\/span>The 8-GPU Standard Domain (2020 to 2022)<\/strong><\/strong><\/span><\/h3>\n\n\n\nFrom the A100 onward, NVIDIA standardized on an 8-GPU building block. A DGX A100 system contains eight A100 GPUs wired to six second-generation NVSwitch ASICs, creating a full-mesh domain in which any GPU reaches any other at 600 GB\/s. The DGX H100 did the same with four third-generation NVSwitch chips, and each H100 keeps its full 900 GB\/s to the fabric.<\/p>\n\n\n\n<\/span>Rack-Scale All-to-All Domains (2024)<\/strong><\/strong><\/span><\/h3>\n\n\n\nThe Blackwell generation changed the unit of scale again. A GB200 NVL72 rack holds 72 GPUs and 36 Grace CPUs, and its nine NVSwitch trays create one 72-GPU NVLink domain. Each GPU in the rack talks to all the others at 1.8 TB\/s, and the fabric aggregates to roughly 130 TB\/s. NVIDIA ships the same 72-GPU domain in two physical layouts: the single-rack NVL72 and the two-rack NVL36x2, which spreads the domain across two cabinets connected by 1.6T OSFP links.<\/p>\n\n\n\n<\/span>External NVLink Domains Beyond One Rack<\/strong><\/strong><\/span><\/h3>\n\n\n\nNVLink does not stop at the rack boundary. NVIDIA sells external NVLink Switch modules, 1U units that each hold two NVSwitch chips and expose OSFP cages, so operators can stitch 8-GPU or 72-GPU domains into larger fabrics. On the DGX H100 generation, external NVLink switches connected up to 256 GPUs at 57.6 TB\/s of aggregate bandwidth. On the Blackwell generation, external NVLink switches link NVL72 racks into even larger NVLink domains for models that will not fit in one rack. These scale-up fabrics are where the biggest and most expensive optical connections appear.<\/p>\n\n\n\n
<\/span>The Evolution of NVLink and NVSwitch<\/strong><\/strong><\/span><\/h2>\n\n\n\n<\/span>2016: Pascal and Tesla P100, First-Generation NVLink<\/strong><\/strong><\/span><\/h3>\n\n\n\nNVIDIA first announced NVLink in 2014, and the technology reached its first product in 2016 with the Tesla P100, built on the Pascal architecture. NVLink 1.0 gave the P100 four links with a bidirectional aggregate of 160 GB\/s, about five times the bandwidth of a PCIe 3.0 x16 slot. This made four- or eight-GPU configurations practical without turning the PCIe bus into the bottleneck. There was no NVSwitch yet; the GPUs talked to each other directly.<\/p>\n\n\n\n<\/span>2017: Volta and Tesla V100, Second-Generation NVLink<\/strong><\/strong><\/span><\/h3>\n\n\n\nThe 2017 Tesla V100, based on Volta, doubled the interconnect story. NVLink 2.0 raised each V100 to six links for 300 GB\/s of bidirectional bandwidth. The DGX-1 with V100 GPUs scaled to eight GPUs using a hybrid mesh, and for the first time NVLink supported GPUs on different PCIe switches, so a single coherent memory space could span a whole node.<\/p>\n\n\n\n<\/span>2018: DGX-2 and the First NVSwitch<\/strong><\/strong><\/span><\/h3>\n\n\n\nThe 16-GPU DGX-2 marked the arrival of NVSwitch. Six first-generation NVSwitch ASICs sat on each baseboard to connect the GPUs, and the switch fabric let any two GPUs in the system exchange data at full NVLink speed. This is the topology that every later NVIDIA system inherits. NVSwitch turned a network of point-to-point links into a real switched fabric.<\/p>\n\n\n\n<\/span>2020: Ampere and A100, Third-Generation NVLink<\/strong><\/strong><\/span><\/h3>\n\n\n\nThe A100 generation standardized the 8-GPU domain. NVLink 3.0 gave each A100 12 links for 600 GB\/s of bidirectional bandwidth, and second-generation NVSwitch chips in the DGX A100 connected eight GPUs into a full-mesh domain. The HGX baseboard that carriers the A100s and their NVSwitches became the reference design that server makers build around, and it is the module a host server plugs into over PCIe.<\/p>\n\n\n\n
<\/span>2022: Hopper and H100, Fourth-Generation NVLink<\/strong><\/strong><\/span><\/h3>\n\n\n\nNVLink 4.0 on the H100 was the first to use PAM4 signaling, jumping per-lane speed to 100 Gb\/s and giving each H100 900 GB\/s across 18 links, roughly 14 times a PCIe 5.0 x16 slot. Third-generation NVSwitch chips brought the SHARP in-network reduction engine to the fabric, so collective operations such as all-reduce run inside the switches. For larger clusters, NVIDIA introduced external NVLink Switch modules that let operators build up to 256-GPU domains, as in the DGX H100 SuperPOD.<\/p>\n\n\n\n<\/span>2024: Blackwell B200, Fifth-Generation NVLink<\/strong><\/strong><\/span><\/h3>\n\n\n\nThe Blackwell generation moved NVLink from a node interconnect into a rack interconnect. NVLink 5.0 gives each B200 1.8 TB\/s across 18 links, and the GB200 NVL72 rack creates a single 72-GPU domain with about 130 TB\/s of fabric bandwidth. NVIDIA also kept improving the NVSwitch: each NVL72 switch tray carries two next-generation NVSwitch ASICs, and the domain spans an entire rack while staying on copper inside the cabinet.<\/p>\n\n\n\n<\/span>2025 to 2026: GB300 Blackwell Ultra<\/strong><\/strong><\/span><\/h3>\n\n\n\nBlackwell Ultra, the GB300 generation, is the volume platform through 2026. The B300 GPU raises memory to 288 GB of HBM3e and pushes the NVL72 rack to roughly 132 kW, and the scale-out network moves to 800G ConnectX-8 network cards. For NVLink itself, GB300 stays on the fifth generation, but the system introduces the copper and optical split that now defines rack design: copper NVLink inside the rack, and optical links wherever the distance grows.<\/p>\n\n\n\n
<\/span>2026: Vera Rubin, Sixth-Generation NVLink<\/strong><\/strong><\/span><\/h3>\n\n\n\nThe Vera Rubin platform brings NVLink 6.0. Announced by NVIDIA in 2025 and detailed through early 2026, NVLink 6 doubles the per-GPU bandwidth to 3.6 TB\/s across up to 36 links per GPU, while the accompanying NVSwitch generation lifts rack-scale fabric bandwidth to roughly 260 TB\/s. The first flagship system, Vera Rubin NVL144, is scheduled to ship in the second half of 2026, and Rubin Ultra (NVL576) follows with co-packaged optics on the roadmap. For anyone buying cables and optics today, this is the transition to watch, because NVLink 6 systems shift more of the fabric to high-speed optical and active electrical cabling.<\/p>\n\n\n\n
<\/span>NVLink vs PCIe: Bandwidth Comparison<\/strong><\/strong><\/span><\/h2>\n\n\n\nIt is easier to appreciate NVLink rates when you compare them to PCIe, the general-purpose bus NVLink was built to bypass. The table uses bidirectional numbers.<\/p>\n\n\n\nInterconnect<\/strong><\/td>Typical peak bidirectional bandwidth<\/strong><\/td>Role<\/strong><\/td><\/tr>PCIe 4.0 x16<\/td> ~64 GB\/s<\/td> General-purpose I\/O<\/td><\/tr> PCIe 5.0 x16<\/td> ~128 GB\/s<\/td> General-purpose I\/O<\/td><\/tr> NVLink 3.0 (A100)<\/td> 600 GB\/s per GPU<\/td> Scale-up within a node<\/td><\/tr> NVLink 4.0 (H100)<\/td> 900 GB\/s per GPU<\/td> Scale-up within a node<\/td><\/tr> NVLink 5.0 (B200)<\/td> 1.8 TB\/s per GPU<\/td> Scale-up within a rack<\/td><\/tr> NVLink 6.0 (Rubin)<\/td> 3.6 TB\/s per GPU<\/td> Scale-up across racks<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\nThe practical consequence is that tensor parallelism and other model-parallel patterns depend on NVLink. When GPUs must exchange weight gradients every training step, an NVLink domain moves that traffic orders of magnitude faster than PCIe could, which is why large-model training effectively requires it.<\/p>\n\n\n\n
<\/span>Why NVLink and NVSwitch Matter for AI and HPC<\/strong><\/strong><\/span><\/h2>\n\n\n\nThree capabilities explain why every major AI cluster now depends on NVLink and NVSwitch:<\/p>\n\n\n\n
\nCoherent shared memory.<\/strong>\u00a0GPUs in an NVLink domain share a unified memory space, so software can treat many accelerators as one large device instead of managing message passing.<\/li>\n\n\n\nNear-linear scale-up.<\/strong>\u00a0A switch fabric gives every GPU-to-GPU pair full bandwidth, so adding GPUs does not throttle communication the way a ring or mesh would.<\/li>\n\n\n\nIn-fabric acceleration.<\/strong>\u00a0Modern NVSwitch generations reduce or eliminate network traffic inside collective operations, cutting the time spent synchronizing across hundreds of GPUs.<\/li>\n<\/ul>\n\n\n\nThe design trade-off is that this power comes with physical constraints. As NVLink bandwidth climbs past 900 GB\/s per GPU, signal integrity and reach start to dictate the design, which is exactly where the cabling and optics decisions in the next section come from.<\/p>\n\n\n\n
<\/span>Cabling and Connectivity: What an NVLink GPU Domain Needs<\/strong><\/strong><\/span><\/h2>\n\n\n\nFor network architects and buyers, the interesting part of the NVLink story is the physical layer, because each generation changed what kind of copper and optical products the fabric uses. This is also where NVLink and the FiberMall portfolio of NVIDIA-compatible transceivers and cables connect.<\/p>\n\n\n\n
<\/span>In-Rack NVLink: Copper Wins<\/strong><\/strong><\/span><\/h3>\n\n\n\nInside a single rack, NVIDIA uses copper for NVLink wherever possible. The GB200 NVL72 runs copper NVLink at the rear of the cabinet, which saves roughly 20 kW per rack compared with optical links and keeps latency low. Those copper runs are high-speed twin-axial cables, essentially large DAC assemblies, that plug into the compute trays and the NVSwitch trays. Copper dominates for NVLink because the distances are short (under a few meters) and the power savings are large.<\/p>\n\n\n\n
<\/span>Rack-to-Rack NVLink: Optics and AECs<\/strong><\/strong><\/span><\/h3>\n\n\n\n