Best fit<\/td> Bursty, statistically multiplexed traffic<\/td> Long-lived, high-bandwidth flows (AI training, DCI)<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\nThe takeaway: OCS does not replace packet switching. It complements it. Most modern hyperscale fabrics use OCS for long-lived, high-bandwidth circuits<\/strong> (such as GPU-to-GPU all-reduce traffic) while keeping packet switches for dynamic, bursty traffic<\/strong> like web requests.<\/p>\n\n\n\n<\/span>How an Optical Circuit Switch Works<\/strong><\/strong><\/span><\/h2>\n\n\n\nThe internal mechanism varies by architecture, but every OCS shares three core elements: an input fiber array, a steering element, and an output fiber array.<\/p>\n\n\n\n
<\/span>3D MEMS Beam Steering<\/strong><\/strong><\/span><\/h3>\n\n\n\n3D MEMS (Micro-Electro-Mechanical Systems) is the dominant technology in large-port-count optical circuit switches. Inside the OCS chassis, two arrays of microscopic mirrors (typically a few hundred micrometers across) are arranged on silicon wafers. Each mirror sits on a tiny gimbal that can tilt on two axes under electrostatic control.<\/p>\n\n\n\n
When a circuit is requested between input port A and output port B:<\/p>\n\n\n\n
\nThe OCS controller calculates the precise tilt angles required for the mirror at position A and the mirror at position B.<\/li>\n\n\n\n Voltage is applied to MEMS actuators, tilting both mirrors.<\/li>\n\n\n\n Light entering port A reflects off mirror A, crosses the free-space optical region inside the chassis, reflects off mirror B, and exits port B.<\/li>\n<\/ol>\n\n\n\nThis is why 3D MEMS scales so well to high port counts. Adding ports means adding more mirrors on the wafer, not adding more switching stages. Modern 3D MEMS OCS systems support 192×192, 320×320, and even larger non-blocking matrices in a single chassis.<\/p>\n\n\n\n
<\/span>Cascaded Optical Matrix<\/strong><\/strong><\/span><\/h3>\n\n\n\nA cascaded optical matrix takes a different approach. Instead of one large free-space region, multiple smaller optical switching stages are connected in series and parallel to build up the total port count. Each stage may use planar lightwave circuits (PLC), liquid crystal optics, or smaller MEMS arrays.<\/p>\n\n\n\n
The cascaded approach trades some insertion loss budget for modularity<\/strong>. You can start with an 8×8 or 16×16 matrix and add stages as your fiber count grows. This is ideal for telecom protection switching, optical lab automation, and progressive data center buildouts where the eventual size is not known on day one.<\/p>\n\n\n\n<\/span>Insertion Loss and Reliability<\/strong><\/strong><\/span><\/h3>\n\n\n\nBoth architectures must hit aggressive insertion loss targets, typically under 3 dB end-to-end, to preserve the optical link budget for downstream coherent or high-baud-rate transceivers. High-quality optical circuit switches use closed-loop feedback (optical taps and photodiodes) to continuously monitor and re-trim mirror positions, compensating for thermal drift and mechanical aging.<\/p>\n\n\n\n
<\/span>Why AI Data Centers Need OCS<\/strong><\/strong><\/span><\/h2>\n\n\n\nThe shift to optical circuit switching is being driven by three forces that all collide inside the AI data center.<\/p>\n\n\n\n
<\/span>1. The Power Wall<\/strong><\/strong><\/span><\/h3>\n\n\n\nA single 800G electrical packet switch can draw 2,000 watts. At hyperscale, the SerDes alone account for a large share of the power budget. Replacing 20% of an electrical fabric with optical circuit switches can reduce total facility power by up to 15%<\/strong> and switching-fabric power by close to 90%, because there is no ASIC and no SerDes in the OCS data path.<\/p>\n\n\n\n<\/span>2. The Latency Wall<\/strong><\/strong><\/span><\/h3>\n\n\n\nAI training workloads spend a surprising fraction of wall-clock time in collective operations like all-reduce. Every nanosecond saved per hop multiplies across thousands of GPUs and millions of iterations. OCS adds essentially zero latency in the data plane, since photons simply traverse glass.<\/p>\n\n\n\n
<\/span>3. The Topology Wall<\/strong><\/strong><\/span><\/h3>\n\n\n\nDifferent AI models prefer different network topologies: ring, torus, fat-tree, dragonfly. With electrical fabrics, the topology is hard-wired into the cabling. With OCS, the topology is defined in software<\/strong>. Reconfiguring an entire training cluster from a fat-tree to a torus can happen in milliseconds through SDN APIs.<\/p>\n\n\n\nThis is exactly why Google’s Apollo, Microsoft’s Sirius, and Meta’s optical fabric initiatives have placed optical circuit switching at the core of their next-generation data center designs.<\/p>\n\n\n\n<\/span>OCS 3D Matrix Switches: Engineering for Scale<\/strong><\/strong><\/span><\/h2>\n\n\n\nThe FiberMall OCS 3D Matrix Switch series targets the core of hyperscale AI factories. Three engineering decisions define the line.<\/p>\n\n\n\n
<\/span>High Port Count<\/strong><\/strong><\/span><\/h3>\n\n\n\nBecause 3D MEMS uses two-axis mirror tilt, a single chassis supports very high port counts (192×192, 320×320, and beyond) without the cabling complexity of a multi-stage architecture. This collapses what would otherwise be racks of electrical Clos fabric into a single optical layer.<\/p>\n\n\n\n
<\/span>Closed-Loop MEMS Control<\/strong><\/strong><\/span><\/h3>\n\n\n\nEach mirror in the matrix is monitored by a feedback loop that tracks its actual position against the commanded position. Drift caused by temperature, vibration, or aging is corrected automatically. The result is a stable optical path that holds calibration over years of continuous operation.<\/p>\n\n\n\n
<\/span>Protocol and Rate Transparency<\/strong><\/strong><\/span><\/h3>\n\n\n\nThe OCS does not see the traffic. A port carrying 400G FR4 today can carry 800G DR8 or 1.6T coherent tomorrow with no hardware change. This protects the capital investment in the OCS chassis even as transceiver technology generations roll forward.<\/p>\n\n\n\n
<\/span>Target Applications<\/strong><\/strong><\/span><\/h3>\n\n\n\n\nGPU-to-GPU fabric<\/strong>\u00a0in AI training clusters where the topology is rebuilt per-job.<\/li>\n\n\n\nData Center Interconnect (DCI)<\/strong>\u00a0links between buildings or campuses where high bandwidth and rate flexibility matter more than per-packet switching.<\/li>\n\n\n\nSpine-layer reconfiguration<\/strong>\u00a0in cloud data centers that want to shift bandwidth between regions or services on a sub-second cadence.<\/li>\n<\/ul>\n\n\n\n<\/span>MOS Cascaded Matrix Switches: Modularity and Cost<\/strong><\/strong><\/span><\/h2>\n\n\n\nFor environments where modularity, density, and cost matter more than maximum port count, the FiberMall MOS Cascaded Matrix Switches deliver a different design point.<\/p>\n\n\n\n
<\/span>Pay-As-You-Grow Architecture<\/strong><\/strong><\/span><\/h3>\n\n\n\nThe cascaded matrix lets operators start with a small matrix and add stages as fiber demand grows. Carriers building optical protection layers, labs automating test fiber setups, and enterprises consolidating cross-connects all benefit from this incremental scaling model.<\/p>\n\n\n\n
<\/span>Redundant Path Protection<\/strong><\/strong><\/span><\/h3>\n\n\n\nFor telecom backbones, the cascaded architecture maps cleanly onto 1+1 and 1:N protection schemes. When a working path fails, the matrix reroutes traffic to a protect path in milliseconds with no impact on upper-layer protocols.<\/p>\n\n\n\n
<\/span>Low Crosstalk<\/strong><\/strong><\/span><\/h3>\n\n\n\nOptical isolation between cascaded stages keeps adjacent paths from interfering, which is critical when many wavelengths or services share a single matrix.<\/p>\n\n\n\n
<\/span>Target Applications<\/strong><\/strong><\/span><\/h3>\n\n\n\n