{"id":3062,"date":"2022-10-28T09:10:34","date_gmt":"2022-10-28T09:10:34","guid":{"rendered":"https:\/\/www.fibermall.com\/blog\/?p=3062"},"modified":"2023-06-25T08:08:09","modified_gmt":"2023-06-25T08:08:09","slug":"800g-optical-module-4x200g-technical-analysis-in-fr-scenario","status":"publish","type":"post","link":"https:\/\/www.fibermall.com\/blog\/800g-optical-module-fr-scenario.htm","title":{"rendered":"800G Optical Module – 4x200G Technical Analysis in FR Scenario"},"content":{"rendered":"

Analysis of technical requirements in 800G FR scenarios<\/b><\/strong><\/span><\/p>\n

The single-channel 200G-based PAM4 technology, a significant phase of next-generation technology for optical intensity modulation and direct detection interconnect, will be the foundation for 4-channel 800G optical connectivity and an essential building block for future 1.6Tb\/s interconnects. As shown in the figure below, the MSA working groups will define the complete PMD and part of the PMA layer specification, including the new low-power, low-latency FEC as a 112G telecom input signal KP4 FEC top package to improve the net coding gain (NCG) of the modem.<\/p>\n

\"Analysis<\/p>\n

One of MSA’s main goals is to develop new broadband, wide-voltage electronic and optical analog components for transmitter and receiver components, including digital-to-analog conversion (DAC) and analog-to-digital conversion (ADC) converters. In order to achieve the low-power goal of pluggable modules, the 200G PAM4 DSP chip will be designed using a lower nm node in the CMOS process, and low-power signal processing algorithms will equalize the channels.<\/p>\n

Considering the need for a Thermo Electric Cooler (TEC) in LAN-WDM, which is not required in the 200G per channel solution, the power budget for the 4x200G 800G solution will be based on CWDM4 to analyze the power. Factors related to the power budget include link insertion loss, multipath interference (MPI), differential group delay (DGD), and transmitter and dispersion penalty (TDP).<\/p>\n

Based on the model published in the IEEE standard, the MPI and DGD penalties are calculated as shown in the table below. Given that the baud increases to 200G per channel, the dispersion penalty will be greater than the dispersion penalty of 100G per channel. A reasonable recommendation for transmitter dispersion penalty (TDP) is .9 dB. Therefore, considering the margins for receiver aging, coupling losses, and the typical transmitter optical power values, the MSA Working Groups believe that the required receiver sensitivity for 200G PAM4 should be around -5 dBm.<\/p>\n

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As the baud doubles from 100G to 200G, the OSNR will deteriorate by about 3 dB. Therefore, a more robust FEC error correction code is required to maintain the receiver sensitivity (-5 dBm) and error floor. Therefore, as mentioned above, the optical module needs to consider encapsulating an additional layer of low-power, low-latency FEC on top of the KP4. The error correction threshold of the new FEC can be determined based on the link performance and power budget requirements. The new FEC will be described later.<\/p>\n

Using simulations and experiments, MSA presents the link performance for a single channel 200G. The following table lists the parameters of the devices used in the link.<\/p>\n

\"the<\/p>\n

The experimental results show that the receiver sensitivity can reach the target value when the new FEC threshold is set to 2E-3 as shown in figure (a) below. However, in this experiment, maximum likelihood sequence estimation (MLSE) is needed to compensate for excessive inter-symbol interference caused by the channel bandwidth limitation.<\/p>\n

\"the<\/p>\n

<\/b>(a) The experimental and simulation results of single-channel 200G match each other; (b) The simulation results of single-channel 200G when the bandwidth of the adopted device is improved: the power budget can be satisfied by using FFE equalization<\/b><\/strong><\/span><\/p>\n

The dashed line in the above figure (a) shows the results of the simulations using the measured parameters of the devices used in the experiments. Combined with the experimental results, the simulation shows that the system is limited by the bandwidth of components such as AD\/DA, drivers, and E\/O modulators. The simulation results based on the same system model (bandwidth expansion) are shown in figure (b) above considering the components that are expected to provide higher bandwidth in the coming years and based on the same system model. The results show that with only FFE equalization in the DSP unit, the receiver sensitivity of 2E-3 can be met, as expected from the theory.<\/p>\n

Based on the above analysis, it is still recommended to follow TDECQ in the compliance test in the 800G-FR4 scheme.\u00a0However, the number of FFE taps of the reference receiver used in the TDECQ measurements needs to be considered to increase to a reasonable value, what exactly needs to be further discussed. In addition, it should be noted that if future capabilities for 100Gbaud optical devices are lower than expected, then more complex algorithms (e.g. MLSE) may need to be used in the FR4 scheme, which means that a new compliance scheme for 800G-FR4 will be necessary.<\/p>\n

4x200G Packaging Solution Analysis<\/b><\/strong><\/span><\/p>\n

For the 4x200G optical module, the packaging of its transmitter and receiver needs to be reconsidered to ensure signal integrity in the range of Nyquist frequency points (56GHz). The following figure shows two possible solutions for the emitter. Scheme A is the traditional scheme, where the modulator driver (DRV) and the modulator (such as EML) are next to each other. In scheme B, the DRV chip based on a flip design is packaged together with the DSP unit to optimize the signal integrity on the RF transmission line. Both solutions can be achieved with existing technologies.<\/p>\n

\"Both<\/p>\n

Preliminary simulations show that Scheme B can achieve good results and ensure a bandwidth greater than 56 GHz.\u00a0The ripple on the S21 curve of Scheme A may be caused by the reflection of the DRV on the input signal, which can be optimized by matching the DRV design to improve the overall performance of Scheme A.<\/p>\n

At the receiver, a high-bandwidth photodiode (PD) with less parasitic capacitance and a high-bandwidth trans-impedance amplifier (TIA) is needed to ensure the bandwidth performance of the receiver. There are currently no obstacles to implementing these components through the most advanced semiconductor technology. As far as we know, the industry has put a lot of effort into developing these components and hopefully they will be available in 1 to 2 years. On the other hand, the connection between PD and TIA is also critical. Parasitic effects in the connection can degrade the performance of the module, which also needs to be carefully analyzed and optimized.<\/p>\n

Forward Error Correction Coding (FEC) in Single Channel 200G<\/b><\/strong><\/span><\/p>\n

As mentioned above, a more powerful FEC is required to meet the sensitivity requirement of the 200G PAM receiver, which is a 2E-3 threshold performance for error correction. The figure below illustrates a comparison between the terminated and concatenated schemes.<\/p>\n

\"800G<\/p>\n

800G FEC: Terminated FEC scheme vs. Concatenated FEC scheme<\/b><\/strong><\/span><\/p>\n

In the first option, KP4 is terminated and replaced by a new FEC with a larger overhead, which has advantages in terms of NCG and overhead. In the second option, the tandem concatenated scheme keeps KP4 as an external code and merges it with the new internal code. This cascaded tandem approach has more latency and power advantages and is therefore more suitable for 800G-FR4 applications.<\/p>\n