<\/span><\/h2>\n\n\n\nXilinx, working with Ranovus for many years, demonstrated a system at OFC2023 that combines Ranovus’ 800G direct-drive silicon photonic engine with AMD’s FPGA chip (Xilinx Versal ACAP). Ranovus has been operating in the CPO field for many years, whose main technical highlights are the use of quantum dot lasers, micro-ring modulators, etc. Ranovus has also started CPO-related cooperation with MediaTek recently and released its latest generation of 6.4TbpsLight Engine.<\/p>\n\n\n\nAMD\/Ranovus<\/strong><\/p>\n\n\n\n<\/span>Broadcom<\/span><\/h2>\n\n\n\nBroadcom demonstrated a 51.2T switch system with CPO at OFC this year. The system contains eight 6.4T FR4 light engine. A single optical engine contains 64 channels of PIC and EIC chips. The driver\/TIA uses CMOS technology with a single-channel signal rate of 100Gbps. The PIC integrates Mux\/DeMux on-chip and operates at CWDM4 wavelength. The light engine uses FOWLP packaging solution, the TSV solution was previously adopted, which may be mainly due to cost and yield considerations. Broadcom has partnered with Tencent to deploy network switches with CPO in its data centers.<\/p>\n\n\n\nBroadcom CPO<\/strong><\/p>\n\n\n\n<\/span>Cisco<\/span><\/h2>\n\n\n\nCisco demonstrated its CPO-based 25.6TSwitch prototype. The system contains eight 3.2T silicon photonic engines, each of which uses eight 400G-FR4 silicon photonic chips, with a single channel rate of 100Gbps, using SISCAP type modulator, with on-chip integrated Mux\/DeMux.<\/p>\n\n\n\nCisco<\/strong><\/p>\n\n\n\n<\/span>IBM<\/span><\/h2>\n\n\n\nIBM is unique in that it did not adopt a silicon photonics solution, but instead worked with Finisar to develop a VCSEL-based CPO system. The system contains 4 PD chips and 4 VCSEL chips. For system reliability considerations, each VCSEL is configured with a redundant VCSEL. The single channel signal rate of it is 56G NRZ, with 16 channels, with a total bandwidth of 896Gbps. The light engine can be connected to the substrate by LGA or welding.<\/p>\n\n\n\nIBM<\/strong><\/p>\n\n\n\n<\/span>Intel<\/span><\/h2>\n\n\n\nIntel has been deeply involved in the field of silicon photonics for many years, and previously focused on the research and development of pluggable optical transceiver and micro-ring modulator technology for silicon photonics. Since 2020, it has started to deploy in the CPO field, targeting Optical Compute Interconnection (OCI), and using its unique silicon photonics process platform to develop a CPO system based on micro-ring modulators. At OFC 2024, the company demonstrated its latest OCI progress. Each PIC has 64 optical channels, the signal rate of a single link is 32Gbps, the overall signal bandwidth is 2Tbps(bidirectional bandwidth is 4Tbps), and link bit error rate is less than 1e-12. In addition, Intel has developed a unique pluggable optical connector, which can screen PIC chips before packaging to improve yield, laying the foundation for large-scale mass production of CPO.<\/p>\n\n\n\nIntel<\/strong><\/p>\n\n\n\n<\/span>Marvell<\/span><\/h2>\n\n\n\nAfter acquiring Inphi, Marvell has greatly enhanced its R&D capabilities in the fields of optical communications and data centers. Marvell launched the latest 6.4T 3D packaged silicon photonic engine at OFC this year, including 32channels, with a single channel signal rate of200Gbps.<\/p>\n\n\n\nMarvell<\/strong><\/p>\n\n\n\n<\/span>Nvidia<\/span><\/h2>\n\n\n\nAs the leader in the GPU field, Nvidia has also been developing silicon photonics CPO technology. At the 2020GTC conference, Nvidia demonstrated a system architecture diagram that interconnects GPU and Switch chips through CPO. In addition, Nvidia is also working with TSMC, Ayar Labs and other companies to develop CPO technology.<\/p>\n\n\n\nSilicon Photonics CPO Technology<\/strong><\/p>\n\n\n\n<\/span>TSMC<\/span><\/h2>\n\n\n\nTSMC began cooperating with Luxtera in 2017 and developed a 12-inch silicon photonics process platform at a 65nm node. It then introduced advanced packaging and launched the COUPE 1.0\/2.0 platform. TSMC recently released its roadmap in the CPO field, which includes the plan to achieve 6.4Tbps light engine by 2025 and further develop 12.8Tbpsoptical engine, used for XPU interconnection.<\/p>\n\n\n\n12-inch silicon photonics platform<\/strong><\/p>\n\n\n\nThe following table summarizes the CPO technologies of the above-mentioned major manufacturers. Currently, except for Broadcom, the solutions of other companies are not strictly CPO, but more like NPO. The optical engines they use are connected to the substrate through an electrical socket, with a certain degree of replaceability. In addition, most manufacturers have chosen the solution of external light source to avoid the influence of internal high-power chip heat dissipation on laser performance.<\/p>\n\n\n\nSummary of demonstrations<\/strong><\/p>\n\n\n\nThe main driving force of CPO technology is its reduction in energy consumption. Since the optical engine is very close to the ASIC chip, the link loss is reduced and there is no need for a retimer chip to compensate the signal between the two, which leads to about 30% reduction of its energy consumption. In addition, CPO technology also improves the bandwidth density of the system.<\/p>\n\n\n\nComparison of retiming approached with laser<\/strong><\/p>\n\n\n\nDoubts about CPO technology and business model have always existed. The following figure is from the PPT of Andy with Arista. Compared with traditional pluggable optical transceiver, the research and development of CPO technology requires in-depth cooperation with major Switch\/XPU manufacturers. The right to speak is mainly in the switch manufacturers, which is not very friendly to small companies. Besides, the CPO module has been criticized for its reliability, testability, and replaceability for a long time, which need to be solved. Since the ASIC chip is packaged together with the CPO light engine, the price of the ASIC chip is very expensive. Once the CPO light engine fails, how can it be repaired or replaced quickly? Sealing optoelectronic chips together also poses challenges to system heat dissipation. The introduction of advanced packaging technologies (TSV, FOWLP, etc.) has, on the one hand, increased R&D costs and prolonged development cycles, and on the other hand, also brought challenges to yield.<\/p>\n\n\n\nThe problems CPO does not solve<\/strong><\/p>\n\n\n\nAs an industry hotspot, CPO technology has received widespread attention from the industry, and major manufacturers are also making their plans. The debate between it and pluggable optical transceiver will continue in the short term. Under the background of AI optical interconnection, the industry may have more stringent requirements for the reliability of optical transceivers. Although CPO technology does have advantages in power consumption and bandwidth density, whether it can be widely used commercially and shake the position of pluggable optical transceivers remains to be discussed. In comparison, Optical IO technology will not take away the market share of pluggable optical transceivers. It can solve the problems of traditional electrical IO in terms of power consumption and bandwidth, thus its promotion may be smoother.<\/p>\n