Technical Requirement Analysis in 800G FR Scenario
PAM4 technology based on single channel 200G is the main part of the next generation technology of light intensity modulation and direct detection interconnection. It will become the foundation of a 4-channel 800G optical connection and an important foundation for future 1.6Tb / s interconnection.
As shown in the figure below, the MSA working group will define the complete PMD and part of the PMA layer specifications. The specifications include the new low-power, low-latency FEC as a package on top of the 112G telecom input signal KP4 FEC to improve the modem’s Net Coding Gain (NCG).
Figure1: Definitions of PMD and PMA specifications
One of the main goals of the MSA Alliance is to develop new wide-bandwidth voltage electronic and optical analog components for transmitter and receiving components, including digital-to-analog (DAC) and analog-to-digital (ADC) converters. To achieve the low power consumption target of pluggable modules, the 200G PAM4 DSP chip will be designed in a CMOS process with a lower nm node, and the channels will be balanced through a low-power signal processing algorithm.
A temperature controller (TEC) is required in LAN-WDM, which is not required in a per-channel 200G solution. Considering this, the power budget of a 4x200G 800G solution will be analyzed based on CWDM4. Factors related to power budget include link insertion loss, multipath interference (MPI), different group delay (DGD), and transmitter and dispersion penalty (TDP).
According to the model published in the IEEE standard, the penalty of MPI and DGD is calculated as shown in the following table. When the baud rate per channel increases to 200G, its dispersion cost will be greater than the dispersion penalty of 100G per channel. The reasonable recommendation for transmitter dispersed penalty (TDP) is 3.9 dB. Therefore, considering the allowance for receiver aging and coupling loss, and the typical emitted optical power of the transmitter, the MSA Working Group believes that the receiver sensitivity required for 200G PAM4 should be around -5dBm.
Table1：Penalty calculation for MPI and DGD
OSNR will deteriorate by about 3 dB due to a double baud rate from 100G to 200G. Therefore, stronger FEC error correction codes are required to maintain receiver sensitivity (-5dBm) and the error floor. As mentioned above, the optical module needs to encapsulate an additional layer of low-power, low-latency FEC on top of the KP4. The error correction threshold for the new FEC can be determined according to the requirements of link performance and power budget.
MSA proposes the link performance of a single channel of 200G through simulation and experiments. The following table lists the parameters of the devices used in the link.
Table2：the parameters of the devices used in the single-channel 200G link
Experimental results show that when the new FEC threshold is set to 2E-3 as shown in Figure (a) below, the receiver sensitivity can reach the target value. However, in this experiment, the maximum likelihood sequence estimation (MLSE) is required to compensate for excessive inter-symbol interference caused by channel bandwidth constraints.
Figure2： Single-channel 200G experiment and simulation results
a) The single channel 200G experiment and emulation results match each other;
(b) When the adopted device bandwidth is improved, the single-channel 200G emulation results: the use of FFE equalization can meet the requirements of the power budget.
The dotted line in figure (a) above shows the results of emulation based on the measurement parameters of the device used in the experiment. Combined with the experimental results, emulation shows that the system is limited by the bandwidth of components such as AD / DA, driver, and E / O modulator. The emulation results are shown in Figure (b) above, which are based on the same system model (bandwidth expansion), considering the components that are expected to provide higher bandwidth in the next few years. The results show that the requirements of receiver sensitivity 2E-3 can be met if there is FFE equalization in the DSP unit, which is in line with theoretical expectations.
Based on the above analysis, in the 800G-FR4 scheme, it is still recommended to follow TDECQ in the compliance test. However, in the TDECQ measurement, the number of FFE taps of the reference receiver may need to be increased to a reasonable value, and the specific amount needs further discussion. In addition, it should be noted that if the capability for 100Gbaud optical devices is lower than expected, more complex algorithms (such as MLSE) may need to be used in the FR4 scheme.
Analysis of 4x200G Package Scheme
For the 4x200G optical module, the package of its transmitter and receiver needs to be reconsidered to ensure signal integrity within the range of the Nyquist frequency point (56GHz). The following figure shows two possible solutions for the transmitter. Scheme A is a traditional scheme, where the modulator driver (DRV) is closely connected to the modulator (such as EML). In Scheme B, the DRV chip based on a flip-chip design is packaged together with the DSP unit to optimize the signal integrity on the RF transmission line. Both solutions can be achieved by the prior art.
Figure3： Two possible solutions for the transmitter
Preliminary emulation shows that scheme B can achieve good results and ensure that the bandwidth is greater than 56GHz. The ripple on the curve S21 of scheme A may be caused by the reflection of the input signal by the DRV, which can be optimized by the matching design of the DRV to improve the overall performance of scheme A.
In RX, a high-bandwidth photo-diode (PD) with less parasitic capacitance and a high-bandwidth trans-impedance amplifier (TIA) is needed to ensure the bandwidth performance of the receiver. At present, there are no obstacles to realizing these components through the most advanced semiconductor technology. As far as we know, the industry has invested a lot of energy in the development of these components and it is hoped that they will be launched within 1 to 2 years. On the other hand, the connection between PD and TIA is also crucial. The parasitic effect in the connection will reduce the performance of the module, so it also needs careful analysis and optimization.
Forward Error Correction Coding (FEC) in Single-Channel 200G
We mentioned above that a more powerful FEC is needed to meet the sensitivity requirements of 200G PAM receivers, that is, the pre-correction error code has the threshold performance of 2E-3. The following figure illustrates the comparison between the terminated scheme and the concatenated scheme.
Figure4：Comparison of Terminated FEC Scheme and Concatenated FEC Scheme
In the first option, KP4 will terminate and be replaced with a new FEC with higher overhead. This scheme has advantages in NCG and overhead. In the second option, the series concatenated scheme retains KP4 as an external code and merges it with the new internal code. This cascaded series method has more advantages in delay and power consumption, so it is also more suitable for 800G-FR4 applications.